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semiconductor group 219 m p interface l 8-bit multiplexed m p-interface (siemens/intel type of m p interface) l 64-byte fifo per channel and direction l efficient transfer of data blocks from/to system memory by interrupt request general l p-dip-28 or p-lcc-28-r package l advanced cmos technology l low power consumption type version ordering code package peb 3035-n v1.1 q67100-h6242 p-lcc-28-r (smd) peb 3035-p v1.1 q67100-h6243 p-dip-28 primary rate interface signaling and maintenance controller (prism) preliminary data cmos ic peb 3035 p-lcc-28-r p-dip-28 features serial interface l two independent signaling/maintenance channels programmable in a C serial mode C strobe mode C time-slot assignment mode l programmable bit inversion l zero bit stuffing l programmable idle code (flags, all ones) l continuous transmission of up to 32-bytes data l data rate up to 4 mbit/s protocol support l support of the esf-dl protocol according to t1.403-1989 or according to at & t tr 54016 l support of hdlc protocol l transparent mode for totally transparent data transmission and reception 01.94
semiconductor group 220 introduction the peb 3035 prism (primary rate interface signaling and maintenance controller) is a two channel serial communication controller designed to support signaling and maintenance functions for t1 - primary rate interfaces using the extended super frame format esf. the device supports the dl-channel protocol for esf format according to t1.403-1989 ansi specification or according to at & t tr 54016, september 1989. the 8-bit parallel m p interface fits perfectly into every siemens/intel 8-bit or 16-bit microcontroller or microprocessor system. the two serial channels can be programmed in three different clock modes to function in time-slot oriented applications, in a strobe mode or as a serial interface. peb 3035
semiconductor group 221 peb 3035 pin configuration (top view) p-lcc-28-r p-dip-28
semiconductor group 222 pin definitions and functions pin no. symbol input (i) output (o) function 25 26 27 28 1 2 3 4 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 i/o data bus the multiplexed address data bus transfers data and commands between the m p interface and the prism. 24 rd i read this signal indicates a read operation. 23 wr i write this signal indicates a write operation. 17 cs i chip select a low on this signal selects the prism for a read/ write operation. 7 10 rxda rxdb i/o i/o receive data , (channel a/channel b) these lines receive serial data at standard ttl or cmos levels. 5 12 rtsa rtsb o o request to send , (channel a/channel b) when rts bit in mode register is set the rts signal goes low. when the rts bit is reset, the signal goes high if the transmitter has finished and there is no further request for transmission. 8 9 txda txdb i/o i/o transmit data , (channel a/channel b) these lines transmit serial data at standard ttl or cmos levels. they can be programmed as push pull or open-drain outputs. 6 11 ctsa ctsb i i clear to send , (channel a/channel b) a change on this input lines leads to an interrupt if enabled (ccr2; cie, see register definitions). 13 res i reset a high on this input forces the prism into reset state. the prism is in power-up mode during reset and in power down mode after reset. the minimum pulse width is 1.8 m s. peb 3035
semiconductor group 223 16 ale i address latch enable a high on this line indicates an address on the external address/data bus. 14 v ss ground (0 v) 15 int od interrupt request the signal is activated when the prism requests an interrupt (active low). int is an open drain output. this pin must be connected to pull-up resistor. 19 18 txclka txclkb i i/o transmit clock , (channel a/channel b) these pins can be programmed in several different modes of operation. t clk may supply - the transmit clock for the respective channel (clock mode 0) - a transmit strobe signal (clock mode 1) - a frame sync. signal (t clka, clock mode 2) programmed as output, the t clkb pin supplies a tristate control signal, indicating the programmed transmit time slot (clock mode 2). 21 20 rxclka rxclkb i i receive clock , (channel a/channel b) these pins can be programmed in several different operation modes. in each channel the r clk pins may supply l the receive clock (clock mode 0) l the receive and transmit clock (clock mode 1, 2). 22 v dd i power + 5 v power supply pin definitions and functions (contd) pin no. symbol input (i) output (o) function peb 3035
semiconductor group 224 block diagram the peb 3035 prism contains two independent, full duplex serial channels which can be used for hdlc signaling, bit oriented messages according to ansi specification t1.403 1989 or fully transparent data communication. the data link controller handles all functions necessary to establish and maintain an hdlc data link, such as C flag insertion and detection, C bit stuffing, C crc generation and checking, C address field recognition. associated with each serial channel is a set of independent command and status registers (sp-reg) and 64-byte deep fifos for transmit and receive direction. peb 3035
semiconductor group 225 peb 3035 functional description the peb 3035 prism is designed to support signaling and maintenance functions for t1 primary rate systems. the device supports the esf-dl channel according to ansi specification t1.403 1989 or according to at & t tr 54016, september 1989. two receivers are implemented in each channel which can be switched on/off independently. if both receivers are activated, prism automatically switches between hdlc and bom mode. the two independent channels can be programmed in three different clock modes to function in time-slot oriented applications, in a strobe mode or as serial interface. 64-byte fifo buffers are used for the temporary storage of data packets transferred between the serial communication interface and the parallel system bus. note: to support the esf-dl protocol according at & t tr 54016, september 1989, or if the prism is used for hdlc format only, the bom receiver has to be switched off. transmission of a preamble of 32 flags before starting an hdlc frame is programmable (ccr1, see register definitions). automatic format switching characteristics: automatic switching between message oriented hdlc and bit oriented messaging (bom) mode, bom and hdlc receiver switched on (mode: hrac, brac). after reset or sw-reset (cmdr: rhr) the prism operates in hdlc mode. if eight or more consecutive ones are detected, the bom mode is entered. upon detection of a flag in the data stream, the prism switches back to hdlc-mode. note: operating in bom-mode, the prism may receive an hdlc frame immediately, i. e. without any preceding flags.
semiconductor group 226 figure 1 switching between hdlc and bom mode hdlc mode receive direction depending on the selected address mode, the prism can perform a 2-byte, 1-byte or no address recognition ( see operating modes ). transmit direction during hdcl operation clock configuration register 1 (ccr1) can be programmed to hdlc interframe timefill mode. either flags or idle as interframe timefill may be selected. (ccr1: itm, it1, it0, see register definitions ). an hdlc frame may now be initiated by the cpu ( see data transmission ). note: an hdlc frame may be transmitted also if bom interframe timefill mode is selected. peb 3035
semiconductor group 227 bom mode receive direction in bom mode, the following byte format is assumed (the left most bit is received first). 11111111 0xxxxxx0 the prism uses the ff h byte for synchronization, the next byte is stored in rfifo (first bit received: lsb) if it starts and ends with a 0. bytes starting or ending with a 1 are not stored. if there are no 8 consecutive ones detected within 32 bit, an interrupt is generated (exir: isf, c.f. 4.2). however, byte sampling is not stopped. byte sampling in bom mode two different bom reception modes may be programmed (mode: brm, see register definitions). 10 byte packets: after storing 10 bytes in rfifo the receive status byte marking a bom frame (rsta: hfr, see register definitions) is added as the eleventh byte and an interrupt (ista: rme) is generated. the sampling of data bytes continues and interrupts are generated every 10 bytes until an hdlc flag is detected. continuous reception: interrupts are generated every 32 bytes (ista: rpf). after detecting an hdlc flag, byte sampling is stopped, the receive status byte is stored in rfifo and an rme interrupt is generated (ista: rme). the user may switch between these modes at any time. byte sampling may be stopped by deactivating the bom receiver (mode: brac). in this case the receive status byte is added, an interrupt is generated (ista: rme) and hdlc mode is entered. whether the prism operates in hdlc or bom mode may be checked by reading the status register (star: bom, see register definitions). 1111 1111 sync 1111 0011 not stored 0100 1111 1111 corrupted new sync sync 0011 0100 1 st byte stored 1110 1111 1 st corrupted sync 0011 0100 2 nd byte stored 1101 1111 2 nd corrupted sync 1111 1111 sync 0111 0110 1 st byte stored 1101 1111 1 st corrupted sync 0111 0110 2 nd byte stored 1111 1111 2 nd sync 0111 0110 3 rd byte stored 0111 1111 3 rd corrupted sync a) b) exir: isf peb 3035
semiconductor group 228 peb 3035 figure 2 reception of a bom frame, example note: yellow alarm bytes are also stored in rfifo. if a bom byte can not be stored due to a full rfifo an interrupt is generated (exir: rfo, see register definitions). yellow alarm detection a yellow alarm condition is indicated by the following byte format: 11111111 00000000 two different algorithms for yellow alarm detection are programmable (yadr: ydm, see register definitions) two of two: yellow alarm is switched on if two yellow alarm indications in sequence are detected. seven of ten: yellow alarm is switched on if at least seven yellow alarm indications out of ten are detected. the mechanism starts immediately after bom mode is entered and checks always the last ten indications received. note: the reception of an hdlc flag resets the yellow alarm search. if the yellow alarm-on condition is detected, the prism generates an interrupt (ista:rsc, see register definitions) and the actual state may be read from status register (star: yal). now the yellow alarm-off detection mechanism is started. yellow alarm is turned off if no yellow alarm indication is received for a programmable number of times (yadr, see register definitions). an interrupt is generated again (ista: rsc) and star: yal may be checked. the yellow alarm/on state can also be cleared by writing the yellow alarm detection register (yadr). note: yellow alarm is not switched off and the yellow alarm-off detection mechanism is not stopped after receiving an hdlc flag, because hdlc flags may be caused by single bit errors on the line.
semiconductor group 229 figure 3 yellow alarm detection, example transmit direction operating in bom mode, clock configuration register 1 (ccr1) may be programmed to bom interframe timefill mode where one of four idle codes may be selected (ccr1: itm, it1, it0 see register definitions). therefore yellow alarm can be issued by programming itm = 1, it1 = 0, it2 = 0. a bom frame may be initiated by the cpu either as a transparent frame or a cyclic transmission frame. in a special transparent transmission mode (mode: txm, see register definitions) the prism generates a sync byte (ff h ) in front of every data byte. therefore only data bytes have to be entered into xfifo, the requested interrupt reaction time is doubled. this mode may also be used with a cyclic transmission frame. note: a transparent frame may also be transmitted with idle or flags as interframe timefill. operating modes the hdlc controller of each channel can be programmed to operate in various modes, which are different in the treatment of the frames in receive direction. thus, the receive data flow and the address recognition features can be effected in a very flexible way, which satisfies a whole variety of requirements. there are 6 different operating modes which can be set via the mode register. 2-byte address comparison the high address byte is compared with three individually programmable values in rah1, rah2 and rah3 registers. bit 1 of the high byte address is excluded from the address comparison of rah1 (7 bit) and is included with rah2 and rah3 (8 bit). the result of the address comparison is stored in the receive status register (rsta:had1,0, see register definitions). peb 3035
semiconductor group 230 peb 3035 similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized when the high and low byte of the address field correspond to one of the compare values. thus, the prism can be called with 8 different address combinations, hdlc frames with address fields not matching one of these address combinations are ignored. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. the hdlc control field and additional information can also be read from special registers (rhcr, rsta). 1-byte address comparison ral the first byte after the opening flag is compared with two individually programmable values in ral1 and ral2 registers. the result of the address comparison is stored in the receive status register (rsta: lad, see register definitions). the whole frame except the address byte plus an additional status byte (rsta) is stored in rfifo. the hdlc control field and additional information can also be read from special registers (rhcr, rsta). 1-byte address comparison rah the first byte after the opening flag is compared with three individually programmable values in rah1, rah2 and rah3 registers. bit 1 is excluded from address comparison of rah1 and is included with rah2 and rah3. the result of the address comparison is stored in the receive status register (rsta:had1,0, see register definitions). the whole frame except the address byte plus an additional status byte (rsta) is stored in rfifo. ral1 contains a copy of the second an rhcr of the third byte following the opening flag. no address comparison no address recognition is performed and each frame will be stored in the rfifo. ral1 contains a copy of the first and rhcr, the second byte following the opening flag. no hdlc framing modes 0, 1 fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc check, bit-stuffing mechanism. data is stored in ral1 register, in mode 1 data is also stored in rfifo. receive data flow (summary) the following figure provides an overview of the hdlc received-frame management under the various operating modes.
semiconductor group 231 figure 4 receive data flow of prism peb 3035
semiconductor group 232 peb 3035 transmit data flow figure 5 transmit data flow of prism for hdlc frames (command xhf via cmdr register), the address and the control fields have to be entered in the xfifo as well. cpu interface register set the communication between the cpu and the prism is done via a set of directly accessible 8-bit registers. the cpu sets the operating modes, controls function sequences, and gets status information by writing or reading these registers (command/status transfer). complete information concerning the register functions is provided in chapter detailed register description. each of the two serial channels of the prism is controlled via an identical, but totally independent register set (channel a and channel b).
semiconductor group 233 interrupt interface special events in the prism are indicated by means of a single interrupt output, which requests the cpu to read status information from the prism, or, if interrupt mode is selected, transfer data from/ to prism. since only one int request output is provided, the cause of an interrupt must be determined by the cpu reading the prisms interrupt status registers (ista, exir). the structure of the interrupt status registers is shown in figure 6. figure 6 prism interrupt status register five interrupt indications can be read directly from the ista register and another six interrupt indications from the extended interrupt register (exir). after the prism has requested an interrupt by setting its int pin to low, the cpu must first read the interrupt status register of channel b (ista-b) in the associated interrupt service routine. the three lowest order bits (bit 2-0) of ista-b (ica, exa, exb) point, if set, to those registers in which the actual interrupt source are indicated. it is possible that several interrupt sources are indicated by a single interrupt request (e.g. if the ica bit is set, at least one interrupt is indicated in the ista register of channel a). an interrupt source from channel b is implicitly indicated by bits 7-3 of ista-b; therefore these bits must also always be checked. the prism interrupt sources can be logically grouped into C receive interrupts, C transmit interrupts, and C special condition interrupts. each interrupt of the ista registers can be selectively masked by setting the respective bit in the mask register. interrupt bit76543210 bit76543210 ista rme rpf rsc xpr tin C C C rme rpf rsc xpr tin ica exa exb exir 0 xdu isf rfo csc rfs C C 0 xdu isf rfo csc rfs C C channel a channel b peb 3035
semiconductor group 234 peb 3035 the following tables give a complete overview of the individual interrupt indications and the cause of their activation. specific restrictions are marked with *. table 1 receive interrupts table 2 transmit interrupts rpf receive pool full (ista) activated as soon as 32 bytes are stored in the rfifo but the message is not yet completed. rme receive message end (ista) activated if either one message up to 32 bytes or the last part of a message with more than 32 bytes is stored in the rfifo. rfo receive frame overflow (exir) activated if a complete frame could not be stored due to occupied rfifo, i.e. the rfifo is full and the prism has detected the start of a new frame. rfs receive frame start (exir) * only activated if enabled by setting the rie bit in ccr2 register. activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. after an rfs interrupt, the contents of C rhcr C ral1 C rsta - bit 3-0 are valid and can be read by the cpu. xpr transmit pool ready (ista) activated whenever a 32-byte fifo pool is empty and accessible to the cpu, i.e. C following a xres command via cmdr, C repeatedly during frame transmission started by xhf command, and no end of message indication (xme command) has been issued yet by the cpu, C after the end-of-message indication when frame transmission of a transparent frame or hdlc frame is completed (i.e. crc and closing flag sequence are shifted out). xdu transmit data underrun (exir) activated if the xfifo holds no further data, i.e. all data has been shifted out via the serial txd pin, but no end of message (eom) indication has been detected by the prism.
semiconductor group 235 table 3 special condition interrupts internal timer external pin fifo structure in both transmit and receive direction 64-byte deep fifos are provided for the intermediate storage of data between the serial interface and the cpu interface. the fifos are divided into two halves of 32-bytes, where only one half is accessible to the cpu at any time. the organization of the receive fifo (rfifo) is such, that in the case of a frame up to 64 bytes long, the whole frame may be stored in the rfifo. after the first 32 bytes have been received, the prism prompts to read the 32-byte block by means of interrupt (rpf interrupt). this block remains in the rfifo until a confirmation is given to the prism acknowledging the transfer of the data block. this confirmation is a rmc (receive message complete) command via the cmdr register. as a result, its possible, to read out the data block any number of times until the rmc command is issued. rsc receive status change activated after a status change of the opposite stations receiver has been detected (yellow alarm on/off). isf incorrect sync format activated if no eight consecutive ones within 32 bits can be detected (bom receiver active). tin timer interrupt (ista) activated if the internal timer has expired (see description of timh, timl register in chapter register description). csc cts status change (exir) * only activated if enabled by setting the cie bit in the ccr2 register. peb 3035
semiconductor group 236 the configuration of the rfifo prior to and after acknowledgement is shown in figure 7. figure 7 configuration of rfifo (long frames) if frames longer than 64 bytes are received, the device will repeatedly prompt to read out 32-byte data blocks via interrupt. in the case of several shorter frames, up to 17 may be stored in the prism. if the accessible half of the rfifo contains a frame i (or the last part of frame i), up to 16 short frames may be stored in the other half (i + 1, , i + n), prior to frame i being fetched from the rfifo. this is illustrated in figure 8 . for a description of a transmit and receive sequence in both interrupt or dma mode, please refer to chapter data transmission and data reception.if frames longer than 64 bytes are received, the device will repeatedly prompt to read out 32-byte data blocks via interrupt. in the case of several shorter frames, up to 17 may be stored in the prism. if the accessible half of the rfifo contains a frame i (or the last part of frame i), up to 16 short frames may be stored in the other half (i + 1, , i + n), prior to frame i being fetched from the rfifo. this is illustrated in figure 8 . peb 3035
semiconductor group 237 figure 8 configuration of rfifo (short frames) note: the number of 17 frames applies for the prism operating in the auto- or non-auto-mode (address recognition), and short frames containing only the hdlc address and control field are received. since the address is not stored, the control field is always stored first in the rfifo, and an additional status byte is always appended at the end of each frame in the rfifo, these frames will occupy two bytes. peb 3035
semiconductor group 238 clock modes the peb 3035 prism can be operated in three different clock modes. l serial mode (clock mode 0) l strobe mode (clock mode 1) l time-slot assignment mode (clock mode 2) table 4 overview of clock modes clock mode 0 (external clocks) separate, externally generated receive and transmit clocks are forwarded to the prism via their respective pins. clock mode 1 (rec./trm. strobes) externally generated, but identical receive and transmit clocks are forwarded via rxclk pins. in addition, a receive strobe can be connected via txclka and a transmit strobe via txclkb pins. this operating mode can be applied in time division multiplex applications. clock type source mode receive clock rxclk pins 0, 1, 2 transmit clock txclk pins rxclk pins 0 1, 2 strobe pulse receive strobe pulse transmit txclka pin txclkb pin 1 1 frame sync. pulse receive, transmit txclka pin 2 peb 3035
semiconductor group 239 peb 3035 clock mode 2 (time slots) this operating mode has been designed for application in time-slot oriented pcm systems. the receive and transmit clock is identical for each channel and must be supplied externally via rxclk pins. the prism receives and transmits only during certain time slots of programmable width (1 256 bit, via rccr and xccr registers) and location with respect to a frame synchronization signal, which must be delivered to the prism via the txclka pin. one of up to 64- time slots can be programmed independently for receive and transmit direction via tsar and tsax registers, and an additional clock shift of 0 7 bits via tsar, tsax, and ccr2 registers. together with bits xcs0 and rcs0 (lsb of clock shift), located in the ccr2 register, there are 9 bits to determine the location of a time slot. according to the value programmed via those bits, the receive/transmit window (time slot) starts with a delay of 1 (minimum delay) up to 512-clock periods following the frame synchronization signal and is active during the number of clock periods programmed via rccr, xccr (number of bits to be received/transmitted within a time slot) as shown in figure 9 . figure 9 location of time slots the transmit time slot is additionally indicated by a control signal via txclkb if enabled via ccr2:tio (active low).
semiconductor group 240 peb 3035 special functions fully transparent transmission the prism supports fully transparent data transmission without hdlc framing overhead, i.e. without l flag insertion and deletion l crc generation and checking l bit-stuffing mechanism data transmission is always performed out of the transmit fifo by directly shifting the contents of the xfifo via the serial transmit data pin (t d). transmission is initiated by setting cmdr:xtf or cmdr: xtf.xme (04 h or 06 h ); end of transmission is indicated by ista:xpr. this feature can be profitably used e.g. for: l user specific protocol variations l transmission of a bom frame l test purposes, intentional violations of hdlc protocol rules (e.g. wrong crc) cyclic transmission (fully transparent) the prism supports the continuous transmission of the transmit fifos contents. after having written 1 to 64 bytes to the xfifo, the command xrep.xtf.xme via the cmdr register (bit 7 0 = 26 h ) forces the prism to repeatedly transmit the data stored in the xfifo via the t d pin. a cyclic transmission is indicated in the star register. a cyclic transmission frame may immediately be added to an other cyclic transmission or transparent frame. transparent frame followed by cyclic transmission: write exactly 32 bytes to xfifo and initiate transmission by setting cmdr:xtf (04 h ). after transmission is started the prism generates an xpr interrupt (ista:xpr). now write 1-32 bytes to xfifo and start cyclic transmission by setting cmdr: xrep.xtf.xme (26 h ). the prism will transmit the first 32 bytes and then will start a cyclic transmission of the second data pool. note: it is also possible to transmit n 32 bytes before starting cyclic transmission. figure 10 transparent frame plus cyclic transmission cmdr:00 h ista: xpr cmdr:26 h cmdr:04 h wr xfifo wr xfifo . . . . . . ista; xpr transparent frame byte 1 C 32 cyclic transmission byte 33 + 34
semiconductor group 241 peb 3035 cyclic transmission sequences: write exactly 32 bytes to xfifo and write cmdr: xrep.xtf (24 h ). the prism starts cyclic transmission and generates an xpr-interrupt (ista: xpr). again 32 bytes may be entered into xfifo. now setting cmdr:xrep.xtf causes the prism to use the second data pool for cyclic transmission and generate an xpr interrupt. this sequence may be repeated. figure 11 cyclic transmission sequences if cmdr:xrep is released, the cyclic transmission is stopped after the last byte in xfifo, after a reset command (cmdr:xres) it is stopped immediately. note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. receive length check feature the prism offers the possibility to supervise the maximum length of received frames and to terminate data reception in case this length is exceeded. this feature is controlled via the special receive length check register (rlcr). the function is enabled by setting the rc (receive check) bit in rlcr and programming the maximum frame length via bits rl6 rl0. according to the value written to rl6 rl0, the maximum receive length can be adjusted in multiples of 32-byte blocks as follows: all frames exceeding this length are treated as if they have been aborted from the opposite station, i.e. the cpu is informed via a C rme interrupt, and the C rab bit in rsta register is set! to distinguish between frames really aborted from the opposite station, the receive byte count (readable from rbch, rbcl registers) exceeds the maximum receive length (via rl6 rl0) by one or two bytes in this case. cyclic transmission byte 33 + 35 cyclic transmission byte 1 C 32 cmdr:00 h ista: xpr cmdr:26 h cmdr:04 h wr xfifo wr xfifo . . . . . . ista; xpr max.length = (rl + 1) 32.
semiconductor group 242 data inversion when nrz data encoding has been selected, the prism may transmit and receive data inverted, i.e. a one bit is transmitted as phys.zero (0 v) and a zero bit as phys.one (+ 5 v) via the txd line. figure 12 this feature is selected by setting the div bit in the ccr2 register. test mode to provide for fast and efficient testing, the prism can be operated in the test mode by setting the tlp bit in the mode register. the on-chip serial input and output (txda C rxda, txdb C rxdb) are connected generating a local loopback. in clock mode 0 the transmit clock is used for reception also. as a result, the user can perform a self-test of the serial channels of the prism. peb 3035
semiconductor group 243 peb 3035 operational description reset the prism is forced into the reset state if a high signal is input to the res pin for a minimum period of 1.8 m s. during the reset period, the prism is temporarily in the power-up mode, and a subset of the registers is initialized with defined values. after reset, the prism is in power-down mode, and the following registers contain defined values: table 5 reset values register reset value meaning ccr1 00 h C power down mode C transmit data pins are open drain outputs C clock mode 0 ccr2 00 h C cts and rfs interrupts disabled no data inversion mode 00 h 1 byte address check C receivers inactive rts output controlled by prism, no testloop star 48 h xfifo write enable receive line inactive no commands executing ista exir 00 h C no interrupts masked cmdr 00 h no commands xccr rccr 00 h 1-bit time slots
semiconductor group 244 initialization after reset the cpu has to write a minimum set of registers and an optional set depending on the required features and operating modes. first, the configuration of the serial port and the clock mode have to be defined via the ccr1 register. the clock mode must be set before power-up, or in the same step with power-up. the cpu may switch the prism between power-up and power-down mode, which has no influence upon the contents of the registers, i.e. the internal state remains stored. in power-down mode however, all internal clocks are disabled, no interrupts are forwarded to the cpu. this state can be used as standby mode, when the prism is temporarily not used, thus considerably reducing the power consumption. the individual operating mode must be defined by writing to the mode register. the need for programming further registers depends on the selected features (clock mode, operating mode, user demands) according to the following tables: table 6 required register address programming for hdlc and bom data reception table 7 user demand registers clock mode register 0, 1 C 2 ccr2, tsar, tsax, xccr, rccr address mode data format 2 byte address field 1 byte address field hdlc rah1, rah2, rah3 ral1, ral2 rah1, rah2, rah3 (mode 101) ral, ral2 (mode 011) bom yadr C yadr transparent C C user demand register cts/rfs interrupt provided ccr2 selective interrupts should be masked mask timer will be used by cpu timl timh receive length check feature rlcr peb 3035
semiconductor group 245 peb 3035 operational phase after having performed the initialization, the cpu switches each individual channel of the prism into operational phase by setting the pu bit in the ccr1 register (power-up, if not already done during initialization). initially, the cpu should bring the transmitter and receiver to a defined state by issuing a xres (transmitter reset) and rhr (receiver reset) command via the cmdr register. if data reception should be performed, the receivers must be activated by setting the hrac/brac bits in mode to 1. now the prism is ready to transmit and receive data. the control of the data transfer phase is mainly done by commands from cpu to prism via the cmdr register, and by interrupt indications from prism to cpu. additional status information, which does not trigger an interrupt, is available in the star register. data transmission in transmit direction 2 32 byte fifo buffers (transmit pools) are provided for each channel. after checking the xfifo status by polling the transmit fifo write enable bit (xfw in star register) or after a transmit pool ready (xpr) interrupt, up to 32 bytes may be entered by the cpu into the xfifo. the transmission of a hdlc frame can then be started by issuing an xhf command via the cmdr register. if the transmit command does not include an end of message indication (cmdr: xme), the prism will repeatedly request for the next data block by means of an xpr interrupt as soon as a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu generates the end of message command (cmdr.xme), after which frame transmission is finished correctly by appending the crc and closing flag sequence. in the case of no more data being available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt (exir: xdu). the frame may also be aborted via software (cmdr: xres). the data transmission sequence, from the cpu's point of view, is outlined in figure 13 .
semiconductor group 246 figure 13 data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (example: frame length = 70 bytes) is shown in figure 14 . peb 3035
semiconductor group 247 figure 14 transmission sequence example data reception two 32-byte fifo buffers (receive pools) are also provided for each channel in the receive direction. there are two different interrupt indications concerned with the reception of data: C rpf (receive pool full) interrupt, indicating that a 32-byte block of data can be read from the rfifo and the received message is not yet complete. C rme (receive message end) interrupt, indicating that the reception of one message is completed, i.e. either l one message with less than 32 bytes, or the l last part of a message with more than 32 bytes is stored in the rfifo. after an interrupt has been processed, i.e. the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issuing an rmc (receive message complete) command. the cpu has to handle the rpf interrupt before additional 32 bytes are received via the serial interface otherwise a receive data overflow condition would occur. in addition to the message end (rme) interrupt, the following information about the received frame is stored by the prism in special registers and/or rfifo: peb 3035
semiconductor group 248 table 8 status information after rme interrupt the following figure gives an example of an interrupt controlled reception sequence in which a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 15 interrupt driven reception sequence example length of message (bytes) rbch,rbcl register address combination and/or rsta register address field ral1 register control field rhcr register type of frame (command/response) rsta register crc result (good/bad) rsta register valid frame (yes/no) rsta register abort sequence recognized (yes/no) rsta register data overflow rsta register peb 3035
semiconductor group 249 detailed register description register address arrangement table 9 layout of register addresses address register comment meaning channel read write ab 00 . . . 1f 40 . . . 5f rfifo xfifo receive/transmit fifo 20 60 ista mask interrupt status/mask 21 61 star cmdr status/command 22 62 mode mode 23 63 timl timer low 24 64 exir timh extended interrupt/timer high 25 65 rbcl rah1 receive byte count low/ receive address high 1 26 66 C rah2 receive address high 2 27 67 rsta rah3 receive status/rec. addr. high 3 28 68 ral1 receive address low 1 29 69 rhcr ral2 rec. hdlc control/rec. addr. low 2 2a 6a C C C 2b 6b C yadr yellow alarm detection register 2c 6c ccr2 channel configuration register 2 2d 6d rbch C receive byte count high 2e 6e vstr rlcr version status/rec. frame length check 2f 6f ccr1 channel configuration register 1 30 70 C tsax time-slot assignment transmit 31 71 C tsar time-slot assignment receive 32 72 C xccr transmit channel capacity 33 73 C rccr receive channel capacity peb 3035
semiconductor group 250 peb 3035 register definitions receive fifo (read) rfifo (00 1f/40 5f) up to 32 bytes of receive data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: exactly 32 bytes to be read rme interrupt: number of bytes to be determined by reading the rbcl, rbch registers. the register set of the peb 3035 prism is based on the sab 82525 hscx. transmit fifo (write) xfifo (00 1f/40 5f) up to 32 bytes of transmit data can be written to the xfifo following an xpr interrupt or star.xfw = 1. note: addresses within the address space of the fifos are interpreted equally, i.e. the actual data byte can be accessed with any address within the valid range. interrupt status register (read) value after reset: 00 h rme receive message end one message of up to 32 bytes or the last part of a message greater then 32 bytes has been received and is now available in the rfifo. the message is complete! the actual message length can be determined by reading the rbch, rbcl registers. additional information is available in the rsta register. rpf receive pool full a block of 32 bytes of a message is stored in the rfifo. the message is not yet completed! rsc receive status change (significant in auto-mode only!) a status change (yellow alarm on/off status of the receiver) has been detected in auto-mode. the current status can be read from the star register (yal bit, bom bit). xpr transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. 70 ista rme rpf rsc xpr tin ica exa exb (20/60)
semiconductor group 251 tin timer interrupt the internal timer has expired. (see also description of timh/timl registers!) ica interrupt of channel a (channel b only) indicates, that an interrupt has been caused by channel a and the interrupt source(s) is (are) indicated in the ista register of channel a (i.e. at least one bit of the ista register of channel a is set). exa extended interrupt of channel a (channel b only) an interrupt has been caused by channel a an the source(s) is (are) indicated in the exir register of channel a. exb extended interrupt of channel b (channel b only) an interrupt has been caused by channel b and the source(s) is (are) indicated in the exir register of channel b. note: the ica, exa and exb bits are present in channel b only and point to the ista (cha), exir (cha), and exir (chb) registers. after the prism has requested an interrupt by turning its int pin to low, the cpu must first read the ista register of channel b and check the state of these bits in order to determine which interrupt source(s) of which channel(s) has caused the interrupt. more than one interrupt source may be indicated by a single interrupt request. after the respective register has been read, exa, and exb are reset. all other bits will be reset after reading ista. to prevent malfunctions, each bit is individually monitored and reset. peb 3035
semiconductor group 252 peb 3035 mask register (write) value after reset: 00 h (all interrupts enabled) each interrupt source can be selectively masked by setting the respective bit in the mask register (bit positions correspond to ista register). masked interrupts are indicated when reading ista. they remain internally stored and will be indicated after the respective mask bit is reset. gim general interrupt mask channel a: if gim is set, all active interrupts of ista cha are indicated but ica is not set in the ista chb. channel b: if gim is set, all active not-masked interrupts of both channels are indicated but the int pin is not turned low. this feature may be used for polling procedures. note: in the event of an extended interrupt, no interrupt request will be generated with a masked exa, exb bit, although this bit is set in ista. 70 mask rme rpf rsc xpr tin gim exa exb (20/60)
semiconductor group 253 extended interrupt register (read) value after reset: 00 h xdu transmit data underrun the actual frame has been aborted with idle, because the xfifo holds no further data, but the frame is not yet complete! note: it is not possible to send frames when an xdu interrupt is indicated. isf incorrect sync format (significant in auto-mode only!) the prism could not detect eight consecutive ones within 32 bits in bom mode. rfo receive frame overflow one frame (hdcl mode) or one byte (bom mode) could not be stored due to occupied rfifo (i.e. a whole frame has been lost). this interrupt can be used for statistical purposes and indicates, that the cpu does not respond quickly enough to an incoming rpf or rme interrupt. csc clear to send status change indicates, that a state transition has occured at the cts pin. the actual state can be read from star register (cts bit). this interrupt must be enabled by setting the cie bit in ccr2. rfs receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. after an rfs interrupt, the contents of C rhcr C ral1 C rsta - bit 3-0 are valid and can be read by the cpu. this interrupt must be enabled by setting the rie bit in ccr2. 70 exir 0 xdu isf rfo csc rfs 0 0 (24/64) peb 3035
semiconductor group 254 peb 3035 status register (read) value after reset: 48 h xdov transmit data overflow more than 32 bytes have been written to the xfifo. xfw transmit fifo write enable data can be written to the xfifo. xrep transmission repeat status indication of cmdr: xrep. yal yellow alarm (significant in auto-mode only!) indicates the yellow alarm status. 0 ... yellow alarm off 1 ... yellow alarm on rli receive line inactive neither flags as interframe time fill nor frames are received via the receive line. note: significant only in point-to-point configurations! cec command executing 0 ... no command is currently being executed, the cmdr register can be written to. 1 ... a command (written previously to cmdr) is currently being executed, no further command can be temporarily written via cmdr register. note: cec will be active at most 2.5-transmit clock periods. if the prism is in power down mode cec will stay active. 70 star xdov xfw xrep yal rli cec cts bom (21/61)
semiconductor group 255 cts clear to send state if the cie bit in ccr2 is set, this bit indicates the state of the cts pin. 0 ... cts is inactive (high signal at cts) 1 ... cts is active (low signal at cts) bom bit oriented message (significant in auto-mode only!) indicates the status of the receiver. 0 ... hdlc mode 1 ... bom mode command register (write) value after reset: 00 h rmc receive message complete confirmation from cpu to prism, that the actual frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. rhr reset receiver all data in the rfifo and the receiver is deleted. xrep transmission repeat together with xtf set (write 24 h or 26 h to cmdr), the prism repeatedly transmits the contents of the xfifo (1 ... 32 bytes) without hdlc framing fully transparent, i.e. without flag, crc insertion, bit stuffing. the cyclic transmission is stopped with an xres command or by resetting xrep. 70 cmdr rmc rhr xrep sti xhf xtf xme xres (21/61) peb 3035
semiconductor group 256 peb 3035 sti start timer the internal timer is started. note: the timer is stopped by rewriting the timl register after start. xhf transmit hdlc transparent frame after having written up to 32 bytes to the xfifo, this command initiates the transmission of an hdlc frame. xtf transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. xme transmit message end indicates, that the data block written last to the transmit fifo completes the actual frame. the prism can terminate the transmission operation properly. xres transmit reset the contents of the xfifo is deleted and idle is transmitted. this command can be used by the cpu to abort a frame currently in transmission. after setting xres an xpr interrupt is generated in every case. note: the maximum time between writing to the cmdr register and the execution of the command is 2.5-clock cycles. therefore, if the cpu operates with a very high clock in comparison with the prism's clock, it's recommended that the cec bit of the star register is checked before writing to the cmdr register to avoid any loss of commands.
semiconductor group 257 mode register (read/write) value after reset: 00 h mds2-0 mode select the operating mode of the hdlc receiver is selected. 000 ... reserved 001 ... reserved 010 ... 1 byte address comparison ral (ral1, 2) 011 ... 2 byte address comparison (rah1, 2, 3 and ral1, 2) 100 ... no address comparison 101 ... 1 byte address comparison rah (rah1, 2, 3) the byte following the address byte is stored in ral1, the third byte is stored in rhcr 110 ... no hdlc framing mode 0 111 ... no hdlc framing mode 1 note: in modes 6 and 7, the hrac and brac bits must be reset to enable fully transparent reception. brm bom receive mode (significant in bom mode only) 0 10 byte packets 1 continuous reception hrac hdlc receiver active switches the hdcl receiver to operational or inoperational state. 0 receiver inactive 1 receiver active in modes 6 and 7 this bit must be reset to enable fully transparent reception! 70 mode mds2 mds1 mds0 brm hrac brac txm tlp (22/62) peb 3035
semiconductor group 258 peb 3035 mode register (read/write) value after reset: 00 h mds2-0 mode select the operating mode of the hdlc receiver is selected. 000 reserved 001 reserved 010 2-byte address comparison (rah1, 2, 3 and ral1, 2) 011 1-byte address comparison ral (ral1, 2) 100 no address comparison 101 1-byte address comparison rah (rah1, 2, 3) 110 no hdlc framing mode 0 111 no hdlc framing mode 1 note: in modes 6 and 7, the hrac and brac bits must be reset to enable fully transparent reception. brm bom receive mode (significant in bom mode only) 0 10-byte packets 1 continuous reception hrac hdlc receiver active switches the hdcl receiver to operational or inoperational state. 0 receiver inactive 1 receiver active in modes 6 and 7 this bit must be reset to enable fully transparent reception! 70 mode mds2 mds1 mds0 brm hrac brac txm tlp (22/62)
semiconductor group 259 brac bom receiver active switches the bom receiver and the yellow alarm detection mechanism to operational or inoperational state. 0 receiver inactive 1 receiver active txm transparent transmission mode 0 full transparent mode; the prism generates one sync-byte (ff h ) and then transmits the content of xfifo. 1 bom transmission mode; a sync byte (ff h ) is generated automatically in front of every data byte. tlp testloop input and output of the hdlc channels are internally connected. in clock mode 0 the transmit clock is used for transmission and reception. (transmitter channel a - receiver channel a/ transmitter channel b - receiver channel b) peb 3035
semiconductor group 260 peb 3035 timer register low (read/write) tv7-0 timer value, bit 7-0 together with bits tv11-8 of timh the time period t 1 is set as follows t 1 = 4 (value + 1) tcp where tcp is the period of C transmit clock (clock mode 0) C receive strobe (clock mode 1) C synchronization signal (clock mode 2) t 1 indicates the time period after which a timer interrupt will be generated. timer register high (write) tmd timer mode a timer interrupt is generated once after the expiration of t 1 (tmd = 0) or periodically (tmd = 1). tv11-8 timer value, bit 11-8 (higher significant bits, refer to description of timl) 70 timl tv7 tv0 (23/63) 70 timh 0 0 0 tmd tv11 tv8 (24/64)
semiconductor group 261 receive byte count low (read) together with rbch (bits rbc11 - rbc8), the length of the actual received frame (1 4095 bytes) can be determined. these registers must be read by the cpu following a rme interrupt. receive address byte high register 1 (write) rah1 value of first individual programmable high address byte. (7 bits compared) bit 1 (c/r-bit) is excluded from address comparison. receive address byte high register 2 (write) rah2 value of second individual programmable high address byte. (8 bits compared) receive address byte high register 3 (write) rah3 value of third individual programmable high address byte. (8 bits compared) 70 rbcl rbc7 rbc0 (25/65) 710 rah1 rah1 0 (25/65) 70 rah2 rah2 (26/66) rah3 rah3 (27/67) peb 3035
semiconductor group 262 peb 3035 receive status register (read) vfr valid frame determines whether a valid frame has been received. 1 valid 0 invalid an invalid frame is either C a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bit), or C a frame which is too short depending on the selected operation mode via mode (mds2, mds1, mds0) as follows: l 16-bit address check: 4 bytes l 8-bit address check: 3 bytes l no address check: 2 bytes note: shorter frames are not reported. rdo receive data overflow a data overflow has occured within the actual frame. crc crc compare/check 0 crc check failed; received frame contains errors. 1 crc check o.k.; received frame is error-free. rab receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the cpu. 70 rsta vfr rdo crc rab had1 had0 lad hfr (27/67)
semiconductor group 263 had1, 0 high byte address compare; significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the prism compares the high byte of a 2-bytes address with the contents of three individual programmable registers (rah1, rah2, rah3). 00 rah3 recognized 10 rah2 recognized 01 rah1, c/r = 0 (bit 1) 11 rah1, c/r = 1 (bit 1) lad low byte address compare; significant only if 2-byte or 1-byte address mode ral has been selected. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two individual programmable registers (ral1, ral2). 0 ral2 has been recognized 1 ral1 has been recognized hfr hdlc frame format a hdlc-frame (hfr = 1) or a bom-frame (hfr = 0) was received. note: rsta7-1 is not valid with a bom-frame (hfr = 0) note: rsta corresponds to the last received hdlc frame; it is duplicated into rfifo for every frame (last byte of frame) peb 3035
semiconductor group 264 peb 3035 receive address byte low register 1 (read/write) the general function (read/write) and the meaning or contents of this register depends on the selected operating mode: C 2-byte/1-byte address comparison - write: ral1 can be programmed with the value of the first individual low address byte. C 1-byte address comparison rah - read: ral1 contains the byte following the high byte of the address in the receive frame (i.e. the second byte after the opening flag). C no address comparison - read: ral1 contains the first byte after the opening flag (first byte of received frame). C no hdlc framing - read: ral1 contains the actual data byte currently assembled at the rxd pin, by passing the hdlc receiver (fully transparent reception without hdlc framing). receive address byte low register 2 (write) value of the second individual programmable low address byte. 70 ral1 ral1 (28/68) 70 ral2 ral2 (29/69)
semiconductor group 265 receive hdlc control register (read) value of the hdlc control field of the last received frame. note: rhcr is duplicated into rfifo for every frame. yellow alarm detection register (write) value after reset: xx h ydm yellow alarm detection mode 0 seven out of ten 1 two out of two yv5-0 yellow alarm off-value, bit 5-0 the number of not-yellow-alarm indications in sequence to declare yellow alarm off are indicated. number = value + 1 note: yellow alarm is turned off by writing yadr 70 rhcr rhcr (29/69) 70 yadr 0 ydm yv5 yv4 yv3 yv2 yv1 yv0 (2b/6b) peb 3035
semiconductor group 266 peb 3035 channel configuration register 2 (read/write) value after reset: 00 h the meaning of the individual bits in ccr2 depends on the selected clock mode via ccr1 as follows: soc special output control 0 data is transmitted on txd, received on rxd pin (normal case) 1 data is transmitted on rxd, received on txd pin. rts request to send defines the state and control of rts pin. 0 the rts pin is controlled by the prism autonomously. rts is activated when a frame transmission starts and deactivated after the transmission operation is completed. 1 the rts pin is controlled by the cpu. if this bit is set, the rts pin is activated immediately and remains active till this bit is reset. tio transmit clock input output switch 0 txclkb pin used as input 1 txclkb pin used as output; in this case the transmit window of channel b is output. note: tio may only be set in ccr2 of channel b cie clear to send interrupt enable any state transition at the cts input pin may cause an interrupt which is indicated in the exir register (csc bit). the actual state at the cts pin can be determined reading the cts bit of the star register. 0 disable 1 enable 70 ccr2 clock mode 0, 1 soc rts 0 0 0 cie rie div (2c/6c) ccr2 clock mode 2 soc rts xcs0 rcs0 tio cie rie div
semiconductor group 267 rie receive frame start interrupt enable when set, the rfs interrupt (via exir) is enabled! div data inversion data is transmitted and received inverted. xcs0, rcs0 transmit/receive clock shift, bit 0 together with bits xcs2, xcs1 (rcs2, rcs1) in tsax (tsar) the clock shift relative to the frame synchronization signal of the transmit (receive) time slot can be adjusted. a clock shift of 0 7 bits is programmable (clock mode 2 only!) received byte count high (read) ov counter overflow more than 4095 bytes received! the received frame exceeded the byte count in rbc11 rbc0. rbc11 rbc8 receive byte count (most significant bits) together with rbcl (bits rbc7 rbc0) the length of the received frame can be determined. 730 rbch 0 0 0 ov rbc11 rbc8 (2d/6d) peb 3035
semiconductor group 268 peb 3035 version status register (read) vn3 vn0 version number of chip 0 sab 82520 hscc 2 peb 3035 prism, version 1.1 receive length check register (write) value after reset: 00 h rc receive check (on/off) 0 receive length check feature disabled 1 receive length check feature enabled rl receive length the maximum receive length after which data reception is suspended can be programmed here. depending on the value rl programmed via rl6 rl0, the receive length is (rl + 1) 32 bytes! a frame exceeding this length is treated as if it was aborted by the opposite station (rme interrupt, rab bit set). in this case, the receive byte count (rbch, rbcl) is greater than the programmed receive length. 730 vstr 0 0 0 0 vn3 vn0 (2e/6e) 730 rlcr rc rl6 rl0 (2e/6e)
semiconductor group 269 channel configuration register 1 (read/write) value after reset: 00 h pu switches between power up and power down mode 0 power down (standby) 1 power up (active) itm interframe timefill mode interframe timefill according hdlc (itm = 0) or bom format (itm = 1). ods output driver select defines the function of the transmit data pins (txda, txdb) 0 txd pins are open drain outputs 1 txd pins are push-pull outputs it1/it0 interframe timefill depending on the selected interframe timefill mode, the following interframe timefill sequences may be selected: l hdlc-mode (itm = 0) 00 continuous idle sequences (txd pin remains in the '1' state) 10 continuous flag sequences (0111 1110 bit patterns) 01 idle sequences, every frame is started with a preamble of 32 flags 11 flag sequences, at least 32 flags are transmitted between two frames note: rts-pin goes low (active) during transmission of a preamble. l bom mode (itm = 1) (leftmost bit transmitted first) 00 11111111 00000000 bit patterns (yellow alarm) 01 11111111 00111000 bit patterns 10 11111111 00110100 bit patterns 11 11111111 00101100 bit patterns cm1, cm0 clock mode selects one of the 3 different clock modes 00 clock mode 0 01 clock mode 1 10 clock mode 2 70 ccr1 pu 0 itm ods it1 it0 cm1 cm0 (2f/6f) peb 3035
semiconductor group 270 peb 3035 time-slot assignment register transmit (write) this register is only used in clock mode 2! tsnx time-slot number transmit selects one of up to 64 possible time slots (00 h -3f h ) in which data is transmitted. the number of bits per time slot can be programmed via xccr. xcs2, xcs1 transmit clock shift, bit 2-1 together with bit xcs0 in ccr2, the transmit clock shift can be adjusted. time-slot assignment register receive (write) this register is only used in clock mode 2! tsnr time-slot number receive defines one of up to 64 possible time slots (00 h -3f h ) in which data is received. the number of bits per time slot can be programmed via rccr. rcs2, rcs1 receive clock shift, bit 2-1 together with bit rcs0 in ccr2, the receive clock shift can be adjusted. 7210 tsax tsnx xcs2 xcs1 (30/70) 70 tsar tsnr rcs2 rcs1 (31/71)
semiconductor group 271 transmit channel capacity register (write) value after reset: 00 h this register is only used in clock mode 2! xbc7 xbc0 transmit bit count, bit 7-0 defines the number of bits to be transmitted with a time slot: number of bits = xbc + 1. (1 256 bits/time slot). receive channel capacity register (write) value after reset: 00 h this register is only used in clock mode 2! rbc7 rbc0 receive bit count, bit 7-0 defines the number of bits to be received within a time slot: number of bits = rbc + 1. (1 256 bits/time slot). 70 xccr xbc7 xbc0 (32/72) 70 rccr rbc7 rbc0 (33/73) peb 3035
semiconductor group 272 peb 3035 electrical specifications absolute maximum ratings dc characteristics t a = 0 to 85 ?c; v dd = 5 v 5%, v ss = 0 v parameter symbol limit values unit ambient temperature under bias t a 0 to 85 ?c storage temperature t stg C 65 to 125 ?c voltage on any pin with respect to ground v s C 0.4 to v dd + 0.4 v maximum voltage on any pin v s 6v parameter symbol limit values unit test condition min. max. input low voltage v il C 0.4 0.8 v input high voltage v ih 2.0 v dd + 0.4 v output low voltage v ol 0.45 v i ol = 7 ma (pins txd, rxd) i ol = 2 ma (all other) output high voltage output high voltage v oh v oh 2.4 v dd C 0.5 v v i oh = C 400 m a i oh = C 100 m a power supply current operational i cc 8ma v dd = 5 v inputs at 0 v/ v dd no output loads power down 1.5 ma input leakage current output leakage current i li i lo 10 m a 0v < v in < v dd to 0 v 0v < v out < v dd to 0 v
semiconductor group 273 capacitance t a = 25 ?c, v dd = 5 v 5%, v ss = 0 v ac characteristics t a = 0 to 85 ?c, v dd = 5 v 5% inputs are driven to 2.4 v for a logical ''1'' and to 0.4 v for a logical ''0''. timing measurements are made at 2.0 v for a logical ''1'' and at 0.8 v for a logical ''0''. the ac testing input/output waveforms are shown below. figure 16 input/output waveform for ac tests parameter symbol limit values unit test condition typ. max. input capacitance c in 510pf output capacitance c out 815pf i/o c io 10 20 pf peb 3035
semiconductor group 274 peb 3035 microcontroller interface timing figure 17 m p read cycle figure 18 m p write cycle figure 19 multiplexed address timing
semiconductor group 275 parameter and values of the bus modes parameter symbol limit values unit min. max. ale pulse width t aa 45 ns address set-up time to ale t al 11 ns address hold time from ale t la 11 ns address latch set-up time wr, rd t als 0ns rd pulse width t rr 120 ns data output delay from rd t rd 120 ns data float delay from rd t df 25 ns rd control interval t ri 60 ns wr pulse width t ww 60 ns data set-up time to wr + cs t dw 30 ns data hold time from wr + cs t wd 10 ns wr control interval t wi 60 ns peb 3035
semiconductor group 276 peb 3035 serial interface timing figure 20 serial interface timing parameter symbol limit values unit min. max. receive data set-up t rds 20 ns receive data hold t rdh 5ns transmit data delay t xdd 20 85 ns request to send delay 1 t rtd1 30 120 ns clock period t cp 240 ns clock period low t cpl 90 ns clock period high t cph 90 ns
semiconductor group 277 clock mode 1 figure 21 strobe timing parameter symbol limit values unit min. max. receive strobe delay t rsd 30 ns receive strobe set-up t rss 60 ns receive strobe hold t rsh 30 ns transmit strobe delay t xsd 30 ns transmit strobe set-up t xss 60 ns transmit strobe hold t xsh 30 ns transmit data delay t xdd 85 ns strobe data delay t sdd 90 ns high impedance from clock t xcz 50 ns high impedance from strobe t xsz 50 ns peb 3035
semiconductor group 278 clock mode 2 figure 22 synchronization timing reset timing parameter symbol limit values unit min. max. sync pulse delay t sd 30 ns sync pulse set-up t ss 30 ns sync pulse width t sw 40 ns time slot control delay t tcd 20 85 ns parameter symbol limit values unit min. max. res high t rwh 1800 ns peb 3035

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